1. Field of the Invention
The present invention relates to an operation method of an SRAM (Static Random Access Memory) device. More particularly, the present invention relates to an operation of a SRAM, which can efficiently perform read/write accessing operations and refresh operation for such SRAM device.
2. Description of the Related Art
Some conventional semiconductor memories, such as dynamic random access memory (DRAM), must be periodically refreshed in order to retain valid data. During refresh operations, external accessing data typically is not allowed. In addition, a mechanism is required to inform the memory controller that the DRAM is performing a refresh operation. Any pending memory transaction has to be delayed until the refresh operation is completed. Refresh operations therefore lengthen the overall access time for memory accesses. It is therefore important to design a memory system in which the impact of refresh operations on external memory access is minimized.
The present invention provides a 2-port memory device, which is necessary periodically, refreshed to maintain the data stored in cells of the memory device is introduced. The memory device can be accessed by read/write operation and a refresh operation without any interference with each other. Such device can provide a very high speed accessing and the operating frequency of the memory device can be easily increased significantly.
To achieve the objective mentioned above, the present invention provides a memory device. The memory device has a plurality of memory cells, each of the memory cells is periodically refreshed to retain a data bit stored in the memory cell. An external clock is applied to the memory device for operation, a first operation clock and a second operation clock being generated by the external clock. The first operation clock is 180-degree phase shift to the second operation clock. The memory device comprises a first word line and a second word line, a first bit line and a second bit line, a first transistor and a second transistor and a storing unit. The first operation clock is applied to the first word line, the second operation clock is applied to the second word line. The first transistor is controlled by the first word line and the second transistor is controlled by the second word line. The storing unit is used for storing the data bit. The storing unit is connected to the first bit line through the first transistor. The first transistor allows the storing unit being connected to the first bit line in accordance with a logic status of the first operation clock. The storing unit is connected to the second bit line through the second transistor. The second transistor allows the storing unit being connected to the second bit line in accordance with a logic status of the second operation clock.
In the above-mentioned memory device, the first transistor and the second transistor are n-channel MOS (NMOS) transistors, and when the logic status of the first operation clock is in a logic high, the first transistor allowing the storing unit being connected to the first bit line, when the logic status of the second operation clock is in a logic high, the second transistor allowing the storing unit being connected to the second bit line.
In the above-mentioned memory device, the first transistor and the second transistor are p-channel MOS (PMOS) transistors, and when the logic status of the first operation clock is in a logic low, the first transistor allowing the storing unit being connected to the first bit line, when the logic status of the second operation clock is in a logic low, the second transistor allowing the storing unit being connected to the second bit line.
To achieve the objective mentioned above, the present invention provides a memory device. The memory device has a plurality of memory cells, each of the memory cells is periodically refreshed to retain a data bit stored in the memory cell. The memory device comprising a first word line and a second word line, a first operation clock being applied to the first word line, a second operation clock being applied to the second word line; a first bit line and a second bit line; a first transistor and a second transistor, wherein the first transistor is controlled by the first word line and the second transistor is controlled by the second word line; and a storing unit, for storing the data bit, the storing unit being connected to the first bit line through the first transistor, the first transistor allowing the storing unit being connected to the first bit line in accordance with a logic status of the first operation clock, the stored data bit being read out or being restored if the storing unit being connected to the first bit line; the storing unit being connected to the second bit line through the second transistor, the second transistor allowing the storing unit being connected to the second bit line in accordance with a logic status of the second operation clock, the stored data bit being refreshed if the storing unit being connected to the second bit line.
It is to be understood that both forgoing general description and the following detailed description are exemplary, and intended to provide further explanation of the invention as claimed.